Tuesday, October 30, 2012

vhdl random number generator for test benches

 LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.math_real.ALL;   -- for UNIFORM, TRUNC functions
  USE ieee.numeric_std.ALL;

tb: process
VARIABLE seed1, seed2: positive;               -- Seed values for random generator
VARIABLE rand: real;                           -- Random real-number value in range 0 to 1.0
VARIABLE int_rand: integer;                    -- Random integer value in range 0..4095
variable time_var1, time_var2: time ;
begin
uniform(seed1, seed2,rand); -- generate random number
int_rand := INTEGER(trunc(rand*4096.0)); -- rescale to 0..4069, find integer part
int_rand := to_integer((to_unsigned(int_rand, 14)) );
time_var2 := (10 ms + (int_rand*1 us)); --save random time n a variable
rand_clock2 <= time_var2; --Save time to a signal so I can see it in waveform
wait for time_var2; --wait for duration random time

end process;

some explaination.....
the uniform function generates a psudo random number.  It is a "real" number so once it is generated the value must be truncated and then converted into an integer.

In this example I chose to turn that integer into a value that would vary the time delays.


References