Latch verse flip-flop

It appears that in a latch, the clock is being used as an enable line which dictates WHEN D should set Q.
ie
Q <= D when enable = '1' else Q;  --latch

It appears that a flip flop, uses the rising edge of the clock to write.  D will set Q when it sees a rising edge.

ie
Q <= D when clock = '1' and clock'event else Q;  --flip-flop

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The below is Reblogged from here

"Latch" Vs "Flip Flop"

Many experienced engineers are clueless about the differences between a "Latch" and a "Flip Flop", and i have seen people using the terms synonymously. I feel that the right use of terminology is very critical in conveying the message more clearly.

I m sure the timing diagrams below is the best way of explanation.

Create logic gates out of muxes

I have created  the AND, OR, NOT, gates using a multiplexer.  With the power of these three you can make all the other logic gates.

Create 2x1 mux out of Nands

It appears to be possible to make a 2 by 1 mux out of NAND Gates.

In the picture below, I have two muxes.  The one on top is a non-simplified version and the bottom is a minimized version.  The non simplified version comes from simply swapping the AND and the OR gates into they NAND equivalents.

Create all basic gates using NANDs

I've always known that you can use several NAND gates to create all the other gates, but never gave much thought as to how it would actually look like.  Here is a picture that I exported from LogiSim.  I created the logic in LogiSim to verify that it is equivalent.

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VHDL

---

function "AND" (A,B:std_logic) return std_logic is
begin
     return (A NAND B)NAND(A NAND B);
end;
---
function "OR" (A,B:std_logic) return std_logic is
begin
     return (A NAND A)NAND(B NAND B);
end;
---
function "NOT" (A:std_logic) return std_logic is
begin
     return (A NAND A);
end;