Verilog Arrays

2d arrays always confuse me, so to save me some headache I'll post what I know about verilog arrays here for reference.

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reg [7:0] w; // bus of width 8.  aka std_logic_vector(7 downto 0);

(picture)
[7][6][5][4][3][2][1][0]

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reg arr [0:3]; // array of size 4 with 1 bit elements. aka array (0 to 3) of std_logic;

(picture)
[0]
[1]
[2]
[3]
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reg [7:0] arr [0:3];// 2d array.  aka array (0 to 3) of std_logic_vector(7 downto 0);

(picture)

key
(...)  --  index
[...]  --  stored value


(7)(6)(5)(4)(3)(2)(1)(0)
[0][1][2][3][4][5][6][7](0)
[8][9][a][b][c][d][e][f](1)
[g][h][i][j][k][l][m][n](2)
[o][p][q][r][s][t][u][v](3)

to access the elements in the array you need to use the operator []

arr[2]; // will give access to row 2. aka return an 8 bit word.
        // will return an value of "ghijklmn"

arr[0][3:2];// will go to row 0 then access columns 3 to 2
            // will return a value of "45"

arr[row][column];
//notes  you can slice a column in to different sizes, but you can only access one row at a time.