Verilog Arrays

2d arrays always confuse me, so to save me some headache I'll post what I know about verilog arrays here for reference.

------------------------------------------------------------------------------------
reg [7:0] w; // bus of width 8.  aka std_logic_vector(7 downto 0);

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[7][6][5][4][3][2][1][0]

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reg arr [0:3]; // array of size 4 with 1 bit elements. aka array (0 to 3) of std_logic;

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[0]
[1]
[2]
[3]
------------------------------------------------------------------------------------

reg [7:0] arr [0:3];// 2d array.  aka array (0 to 3) of std_logic_vector(7 downto 0);

(picture)

key
(...)  --  index
[...]  --  stored value


(7)(6)(5)(4)(3)(2)(1)(0)
[0][1][2][3][4][5][6][7](0)
[8][9][a][b][c][d][e][f](1)
[g][h][i][j][k][l][m][n](2)
[o][p][q][r][s][t][u][v](3)

to access the elements in the array you need to use the operator []

arr[2]; // will give access to row 2. aka return an 8 bit word.
        // will return an value of "ghijklmn"

arr[0][3:2];// will go to row 0 then access columns 3 to 2
            // will return a value of "45"

arr[row][column];
//notes  you can slice a column in to different sizes, but you can only access one row at a time.

Verilog vs VHDL

UCR started me off with VHDL.  It was definately a struggle to learn how to avoid all the little errors.  The errors were of course my own fault for not realizing the nature of how hardware logic works.  Software does things differently then hardware does it, and I struggled with vhdl until I had learned the differences.  In the end, I developed a fondness for the HDL.

After graduation, it was up to me to decide my education.  My self taught education.  Verilog was the popular HDL in america and it would be a good idea to learn it since that is where everyone is at.  I gave it a shot and to my surprise, it was vastly more easy.  It probably has more to do with my experience with vhdl then the simplicity of the language.  I had already understood hardware so it was easy to learn the new language.

The two languages are essentially two different interfaces with the same thing.

The basic components like AND, REG, and COUNTER were finished with ease.  But I discovered a problem when I tried synthesising the counter.

Here is a snippet of code
==========
...

wire [WIDTH-1:0] reg2adder_w, adder2reg_w;

sreg_gen #( .WIDTH(WIDTH))
sreg(
.clock(clock), .reset(reset), .en(enable),
.data_i( adder2reg_w),
.data_o( reg2adder)
);
assign count = reg2adder;

...
=====
end snippit


look at the snippit and tell me if you see a problem.......got it? there is no wire named"reg2adder".  It was a typo and verilog responds by giving me warnings.  It responds by implicitly creating a wire called "reg2adder" of bitwidth 1.  So it gives me warnings telling me that the data_o is 32 bits and it is trying to shove it into reg2adder which is 1 bits.  This makes 31 of data_o's bits unconnected!

In VHDL, this would have turned out differently.  In VHDL it would have simply said something along the lines of "ERROR:reg2adder not declared".  Thats a much easier explanation then the warning I had recieved for verilog .

I've heard that verilog tends to sweep errors under the rug, but I didn't think it would make a mistake on something so simple.....

So the moral of the story is to make sure that you are using the right wire names cause apparently, verilog won't catch it for you.

VHDL one.... Verilog zero....