vhdl random number generator for test benches

 LIBRARY ieee;

  USE ieee.std_logic_1164.ALL;

  USE ieee.math_real.ALL;   -- for UNIFORM, TRUNC functions

  USE ieee.numeric_std.ALL;

tb: process

VARIABLE seed1, seed2: positive;               -- Seed values for random generator

VARIABLE rand: real;                           -- Random real-number value in range 0 to 1.0

VARIABLE int_rand: integer;                    -- Random integer value in range 0..4095

variable time_var1, time_var2: time ;

begin

uniform(seed1, seed2,rand); -- generate random number

int_rand := INTEGER(trunc(rand*4096.0)); -- rescale to 0..4069, find integer part

int_rand := to_integer((to_unsigned(int_rand, 14)) );

time_var2 := (10 ms + (int_rand*1 us)); --save random time n a variable

rand_clock2 <= time_var2; --Save time to a signal so I can see it in waveform

wait for time_var2; --wait for duration random time

end process;

some explaination.....

the uniform function generates a psudo random number.  It is a "real" number so once it is generated the value must be truncated and then converted into an integer.

In this example I chose to turn that integer into a value that would vary the time delays.

References

http://www.markharvey.info/vhdl/rnd/rnd.html

Verilog Arrays

2d arrays always confuse me, so to save me some headache I'll post what I know about verilog arrays here for reference.

------------------------------------------------------------------------------------
reg [7:0] w; // bus of width 8.  aka std_logic_vector(7 downto 0);

(picture)
[7][6][5][4][3][2][1][0]

------------------------------------------------------------------------------------
reg arr [0:3]; // array of size 4 with 1 bit elements. aka array (0 to 3) of std_logic;

(picture)
[0]
[1]
[2]
[3]
------------------------------------------------------------------------------------

reg [7:0] arr [0:3];// 2d array.  aka array (0 to 3) of std_logic_vector(7 downto 0);

(picture)

key
(...)  --  index
[...]  --  stored value


(7)(6)(5)(4)(3)(2)(1)(0)
[0][1][2][3][4][5][6][7](0)
[8][9][a][b][c][d][e][f](1)
[g][h][i][j][k][l][m][n](2)
[o][p][q][r][s][t][u][v](3)

to access the elements in the array you need to use the operator []

arr[2]; // will give access to row 2. aka return an 8 bit word.
        // will return an value of "ghijklmn"

arr[0][3:2];// will go to row 0 then access columns 3 to 2
            // will return a value of "45"

arr[row][column];
//notes  you can slice a column in to different sizes, but you can only access one row at a time.

Verilog vs VHDL

UCR started me off with VHDL.  It was definately a struggle to learn how to avoid all the little errors.  The errors were of course my own fault for not realizing the nature of how hardware logic works.  Software does things differently then hardware does it, and I struggled with vhdl until I had learned the differences.  In the end, I developed a fondness for the HDL.

After graduation, it was up to me to decide my education.  My self taught education.  Verilog was the popular HDL in america and it would be a good idea to learn it since that is where everyone is at.  I gave it a shot and to my surprise, it was vastly more easy.  It probably has more to do with my experience with vhdl then the simplicity of the language.  I had already understood hardware so it was easy to learn the new language.

The two languages are essentially two different interfaces with the same thing.

The basic components like AND, REG, and COUNTER were finished with ease.  But I discovered a problem when I tried synthesising the counter.

Here is a snippet of code
==========
...

wire [WIDTH-1:0] reg2adder_w, adder2reg_w;

sreg_gen #( .WIDTH(WIDTH))
sreg(
.clock(clock), .reset(reset), .en(enable),
.data_i( adder2reg_w),
.data_o( reg2adder)
);
assign count = reg2adder;

...
=====
end snippit


look at the snippit and tell me if you see a problem.......got it? there is no wire named"reg2adder".  It was a typo and verilog responds by giving me warnings.  It responds by implicitly creating a wire called "reg2adder" of bitwidth 1.  So it gives me warnings telling me that the data_o is 32 bits and it is trying to shove it into reg2adder which is 1 bits.  This makes 31 of data_o's bits unconnected!

In VHDL, this would have turned out differently.  In VHDL it would have simply said something along the lines of "ERROR:reg2adder not declared".  Thats a much easier explanation then the warning I had recieved for verilog .

I've heard that verilog tends to sweep errors under the rug, but I didn't think it would make a mistake on something so simple.....

So the moral of the story is to make sure that you are using the right wire names cause apparently, verilog won't catch it for you.

VHDL one.... Verilog zero....

Using screen to send serial communication rs232 at 9600 baud rate

A few weeks ago, I found a great method for sending and receiving serial data.

When I did the UART lab in school we used cute com in order to send and receive a byte of information.  for example, if I entered "Hello" in to the cute com, it would send something through the usb.  The usb would enter the nexus 3 spartan6 board.  some magic would happen and then it would send back the message through the usb and into the pc.  then cutecom would show"Hello" again.

ie "HelloHello"

The problem was that I was using a mac and at the time I had no idea how to do something like cute com.  I know about the existence of mini com but I did not want to download it.  In the back of my mind I thought that this would be a great opportunity for me to make my own "mini com", but the question what how?  I had many fruitless googling until I stumbled upon "screen".

Apparently "screen" could be used instead of "mini com" .  This was great news!  I'm not going to go into the technical details of how I interfaced my fpga with my mac book pro (10.7) because I had covered that in a past post.

Question....How to use screen?  It isn't hard.  After you plug it in you type this into the terminal without the quotes.
"screen <usbserial_com> <baud_rate>"

in my case the usbserial_com was "/dev/tty.usbserial-A700h2To"
and my baud rate "9600"

ie.
"screen /dev/tty.usbserial-A700h2To 9600"

How do I test if it works?
I pulled out one of my old UARTio labs from the past.  All it did was receive and transmit.  It was an unfinished project where I was suppose to add keyboard functionality to it, but I never got around to it. Luckly, my procrastination turned out for the better, cause now I could simply compile what I had without having to change anything.

I compiled it, and programmed the fpga. flipped the switches.
I ran the screen command that I mentioned above.

at first it looked like an empty terminal.

I typed "a" and I recieved an "a".  I turned off the fpga and typed "a" again. nothing happened.
So the uartio was working correctly.  I type something in, it goes to the fpga then pops back to the terminal.  SWEET.

ok, what about a more realistic solution?  eventually I would write a program that would read in an image (i.e. bmp)  and send some info through the usb and write somewhere on the   fpga memory.

So at first i thought I could write a c++ program that would run "screen"
But as it turns out, most programs wouldn't do that.

Eventually I found this neat site from arduino.  It was meant for serial compunication with an arduino, but oh well, same difference.
http://todbot.com/arduino/host/arduino-serial/arduino-serial.c

Here is a link to more languages.
http://www.arduino.cc/playground/Main/InterfacingWithSoftware


As of now, I'm using the  "C" version.  Reason being that it is useful for osx/windows/linux.
The only problem is that I haven't quite figured out how it works.  After tracing it with my eyes, I tried distilling the most essential parts so that I could make my own dedicated program.  I failed.  for now, But eventually I'll get it.

So then I tried using the Arduino C code as is and it actually worked.
ie ./a.out -b 9600 -p /dev/tty.usbserial-A700h2To -s 3; //actually sends the ascii version of 3.

Oh yeah, the data I send to the fpga shows up on the 8 led's so I can verify what is being sent.

TMR I will go through the program more carefully and trace its path.  I WILL find out how to write my own.

bram timing

I went ahead and played with Isim because I wanted to find out how long it would take for a value to be written to the bram data.

So I opened the ip generator and selected block ram.

16 wide and 16 tall.

I hooked up the DCM and tested it to see what would happen.

oh yeah, the DCM needs some special configurations.  Instead of going blah blah, I'll just copy and past it right here

-------

   DCM_CLKGEN_inst : DCM_CLKGEN
   generic map (
      CLKFXDV_DIVIDE => 2,       -- CLKFXDV divide value (2, 4, 8, 16, 32)
      CLKFX_DIVIDE => 1,         -- Divide value - D - (1-256)
      CLKFX_MD_MAX => 0.0,       -- Specify maximum M/D ratio for timing anlysis
      CLKFX_MULTIPLY => 256,       -- Multiply value - M - (2-256)
      CLKIN_PERIOD => 0.0,       -- Input clock period specified in nS
      SPREAD_SPECTRUM => "NONE", -- Spread Spectrum mode "NONE", "CENTER_LOW_SPREAD", "CENTER_HIGH_SPREAD",
                                 -- "VIDEO_LINK_M0", "VIDEO_LINK_M1" or "VIDEO_LINK_M2"
      STARTUP_WAIT => FALSE      -- Delay config DONE until DCM_CLKGEN LOCKED (TRUE/FALSE)
   )
   port map (
      CLKFX => CLKFX,         -- 1-bit output: Generated clock output
      CLKFX180 => CLKFX180,   -- 1-bit output: Generated clock output 180 degree out of phase from CLKFX.
      CLKFXDV => CLKFXDV,     -- 1-bit output: Divided clock output
      LOCKED => open,       -- 1-bit output: Locked output
      PROGDONE => open,   -- 1-bit output: Active high output to indicate the successful re-programming
      STATUS => open,       -- 2-bit output: DCM_CLKGEN status
   
CLKIN => clock,         -- 1-bit input: Input clock
      FREEZEDCM => '0', -- 1-bit input: Prevents frequency adjustments to input clock
      PROGCLK => open,     -- 1-bit input: Clock input for M/D reconfiguration
      PROGDATA => open,   -- 1-bit input: Serial data input for M/D reconfiguration
      PROGEN => open,       -- 1-bit input: Active high program enable
      RST => '0'              -- 1-bit input: Reset input pin
   );

-------

ok, to make a long story short, the multiplied clock signal shall be called "clkfx"
The not clock is called "clkfx180".

I write using the rising edge of clkfx180.  I read using the rising edge of "clkfx"
This is mainly for the VGA screen.  The timer needs to be in synce with read.

So anyways, how long DOES it take to write to the memory?
well, when I ramp the multiplier to 256, it takes 0.000144 us.
The down side was that clkfx must tick 5 times.

mult | time(ns) | clkfx ticks
256 | 0.144  | 5
128 | 0.183 | 3
64  | 0.183 | 2
32  | 0.339 | 2
16  | 0.724  |2

it seams like 64 multiplier seems to be the best choice.  I just have to make sure that I hold the data value and the write enable needs to be held for 2 ticks.

lets say it takes 0.2 ns to write.  How long will it take to clear the pixel mem?
The pixel mem has 320*240 = 76800 addresses.

0.2ns*76800 = 15360ns

--
perhaps I want the print to clear ratio to be 999:1

0.0153 sec or  15 ms will be spend printing .

this would have ~ 60hz period of writing and clearning.

Hopefully with this config, I would be able to get rid of the flicker the plagues my project.

-----
The duty is low, it shall work for the duration of 15360ns.
the duty will be high for the durations of 15 ms.

good exercices to do

This is for a computer architechture classes and I found their labs quite useful for practicing

http://students.cse.tamu.edu/wanglei/csce350/handout/lab6.html

Latch verse flip-flop

It appears that in a latch, the clock is being used as an enable line which dictates WHEN D should set Q.
ie
Q <= D when enable = '1' else Q;  --latch

It appears that a flip flop, uses the rising edge of the clock to write.  D will set Q when it sees a rising edge.

ie
Q <= D when clock = '1' and clock'event else Q;  --flip-flop

---------
The below is Reblogged from here

"Latch" Vs "Flip Flop"

Many experienced engineers are clueless about the differences between a "Latch" and a "Flip Flop", and i have seen people using the terms synonymously. I feel that the right use of terminology is very critical in conveying the message more clearly.

I m sure the timing diagrams below is the best way of explanation.

Create logic gates out of muxes

I have created  the AND, OR, NOT, gates using a multiplexer.  With the power of these three you can make all the other logic gates.

Create 2x1 mux out of Nands

It appears to be possible to make a 2 by 1 mux out of NAND Gates.

In the picture below, I have two muxes.  The one on top is a non-simplified version and the bottom is a minimized version.  The non simplified version comes from simply swapping the AND and the OR gates into they NAND equivalents.

Create all basic gates using NANDs

I've always known that you can use several NAND gates to create all the other gates, but never gave much thought as to how it would actually look like.  Here is a picture that I exported from LogiSim.  I created the logic in LogiSim to verify that it is equivalent.

---

VHDL

---

function "AND" (A,B:std_logic) return std_logic is
begin
     return (A NAND B)NAND(A NAND B);
end;
---
function "OR" (A,B:std_logic) return std_logic is
begin
     return (A NAND A)NAND(B NAND B);
end;
---
function "NOT" (A:std_logic) return std_logic is
begin
     return (A NAND A);
end;

install windows on osx bootcamp partition using boot camp

I have found a wonderful, in depth guide to installing windows on the boot camp partition on your osx machine.  It uses a trick in parallels and it appears to be more successful then doing it with vmware.

Here is the link to the tutorial: 

The writer of the tutorial says that you have to modify the master boot record (MBR) which can be tricky if you aren't familiar with using the terminal.  (There is also that feeling of messing with something that you don't really understand....)

Here is the link to the forum I found the link in:

According to the original poster, you can install it without fiddling around with the mater boot record.  All you need is to install rEFIt and I guess it will magically find the windows partition.

It is unknown whether he quit parallels as per the tutorial or let it completely install, before restarting his computer to boot windows.

spartan 6 uart

After downloading the drivers I tried to find the FTD in the "/dev/tty.*"

I did not find it.  However after I plugged in the FPGA's uart something new appeared.

typing "/dev/tty.*" revealed a new port:

/dev/tty.usbserial-A700h2To

When I unplug it, the port disappears and when I plug it back in, it reappears.

in this example, it shows a port that contains the characters "...ftd..."

This tells me that either the company decided to use a radically new name

OR

I didn't really need to download the driver.

One way I can find out is by plugging it in to my other mac to see if it shows up.

what ever the answer is, it isn't a big deal.  what IS a big deal is that I am able to send and receive information from this port.

UPDATE:
I tried pluging in my spartan 6 uart to my other mac but the usbserial-A7.... did not appear.
However, after installing the driver, it appeared.

So yes, the Driver IS necessary.

osx serial communication using "screen" command in terminal

UPDATE
*Apparently minicom would be the osx equivalent to cutecom.
*USB to serial communication has many different drivers. and it all depends on what chip is being used.  I used to find a lot of site talking about a usb to rs232 wire and what made the wire work was a small chip inside of it.  Two big companies made those chips, PL and FTD.  In order to do serial com in terminal you first need the right drivers.  The driver must be the one for the corresponding chip.
Since I was using a spartan 6 I had to take a look at the documentation to find out which chip.  When I plugged it in to my windows machine, it would automatically download the drivers so I never gave it much of a thought.  However, I do not believe osx does this.  The spartan 6 documentation said that the uart had a ftd chip so I went ahead and downloaded the osx driver.
===============
In linux we have cutecom.
In windows we have hyperterminal/terminte
of osx, we have neither.

The purpose of these programs is to help will serial communication such as rs232 protocol.
In my UART fpga lab i had to send a byte of data to the cutecom.  If I did
the protocol correctly, the byte would show up on the screen.
(i.e. fpga sends the char "x" the cutecom shows x)
The reverse also works.  The cutecom can send the fpga the byte
(i.e. cutecom sents char "Z" the fpga shows "Z" in the led's)

I really do wonder why there isn't a nice program for osx.  After searching for it on google
it appears that there are special adapters for rs232 to usb.  Its not really what I was looking for.

IF there was no program like cutecom then there had to be at least SOME way to communicate with the
usb com.

Apparently  you can use the actual terminal

http://www.tigoe.net/pcomp/resources/archives/avr/000749.shtml

I believe a good side project would be to create your very own "cutecom" for the osx.
You would have to figure out how to use it though.....

look into it by using "man screen"

--===========================
--original doc reproduced below
-------------------------------------------

Serial Communication in OSX Terminal

I knew it had to be possible to view serial data in the OSX terminal window, but I'm not enough of a unix geek to figure it out. Finally, a little googling told me what I needed to know. Here's how to read and send serial data from the terminal in OSX.
First, open Terminal. If you've never used it before, it's under Applications/Utilities/Terminal. Next, type

ls /dev/tty.*

to get a list of all of your serial ports. Pick the one that you want to open. For example, my list looks like this:

/dev/tty.BTRS232                        /dev/tty.Tigoe6630-AppleAgent-1
/dev/tty.Bluetooth-Modem                /dev/tty.Tigoe6630-Dial-UpNetwor-2
/dev/tty.KeySerial1                     /dev/tty.modem

And I know from previous experience that /dev/tty.Keyserial1 is my Keyspan USB-to-serial adaptor. It's connected to a PIC at the moment. The PIC's programmed to read one byte of serial data at 9600 bits per second, then send back three bytes, "A", "B" and "C".
Knowing the serial port, you can just type screen portname datarate to show the serial data on the screen. In my case, it was:

screen /dev/tty.Keyserial1 9600

Then I started typing bytes at the PIC, and it sent bytes back to me. Whee! No need for zTerm! To quit the screen app, tyoe control-A, then control-\.

how to install windows without dvd drive

you can use VMWARE to install it into the boot camp parition

http://forums.macrumors.com/showthread.php?t=601414

I haven't tested it personally, but from the looks of it, the people in the forum say they were able to get it to work.  The answer is in the post by colin which is reproduced below.

=====================================

I'm working on installing Windows 7 without a DVD (broken SuperDrive here) using VMWare Fusion and the instructions provided by melchior.

I think I've figured out a way to make VMWare install Windows 7 to the Boot Camp partition.

I'll try and see if it works, and if it does I will post instructions.

Edit:

Great news, I got the Boot Camp partition to show up in VMWare Fusion when installing windows. I'm going to install it! 

Here's what I did:

Step 1: Installed VMWare, opened up the application to make sure everything worked correctly, then quit.

Step 2: I created a folder in the root of my hard drive (Macintosh HD) entitled "Virtual Machines"

Step 3: I typed the following into Terminal:

Code:

cd /Virtual\ Machines

Then..

Code:

/Library/Application\ Support/VMware\ Fusion/vmware-rawdiskCreator print /dev/disk0

A list of my computer's partitions appeared, then I typed..

Code:

/Library/Application\ Support/VMware\ Fusion/vmware-rawdiskCreator create /dev/disk0 3 windows7 ide

You can see a screenshot of Terminal after typing in these commands below.

After that, I opened up VMWare Fusion. I chose to make a new machine, I hit Continue Without Disc.

I chose Use existing virtual disk, then selected windows7.vmdk out of the Virtual Machines folder in root of Macintosh HD. 

VMWare asked me if I wanted to convert the disk into an "updated" version, I chose not to convert the disk image.

After that, I unchecked "automatically open machine when VMWare starts", then hit finish. I opened up the settings for the newly created virtual machine, and changed the disc to point to my Windows 7 ISO file.

I started the machine, and VMWare successfully recognized my Boot Camp partition and I'm installing Windows 7 onto the partition right now.


Screenshot of Terminal after typing in commands:



Update:

Setup completed successfully in VMWare and rebooted. I'm going to try and natively boot off of this, if it doesn't work I'll try winclone (I think winclone might set the partition to active when it copies the flies to the partition, that's why that "trick" causes the partition to become bootable again).

Side note: The reason why you type disk0 into Terminal instead of the actual ID of the Boot Camp partition (usually it's disk0s3) is because the VMWare Raw Disk Creator considers the Boot Camp partition a "special" partition and tags it with a 0 rather than using the usual disk0s3 stuff.

Attaching bram to vga

The VGA is working and as a hard coded test, I created some colorful squares
using
rgb_o <= "111" when within_range else "000";

Now it is time to use something that has the potential to change over time.

I used a BRAM to store the color values for each pixel.
Although I wasn't about to harness 8 bit color, at least I was able to get 3 bit color.

I hard coded a few colors into the bram and viola! they showed up in the screen!

below is the state machine I used to test my bram.  The purpose of this
state machine is to  add things to the BRAM and then the VGA timer would read that bram.
This snippit of code only showes how I added something new to the bram.

The screen showed 3 squares of the expected size.  However, there were some random artifacts such as dots being missing or dots being missing colored or dots being in places where they shouldn't.  I believe that
it is mainly a side effect of a poorly written process.  The snippit below was meant to be quick and dirty, so it is rather unorthodox.
--==========================================

process(clock)
constant max_val: integer := (hdisp_size*vdisp_size);
variable cnt: integer:= 0;
variable color_var: std_logic_vector(2 downto 0):= (others => '0');
type states is (init,x_sq, y_sq);
variable st: states := init;
variable x_var,y_var: integer:= 0;
variable coordinate:integer:= 0;
begin
if clock = '1' and clock'event then
case st is
when init => st := x_sq;
when x_sq =>
if x_var >= hdisp_size then st:= y_sq;
x_var := 0;
else st:= x_sq;
x_var := x_var + 1;
end if;
when y_sq =>
if y_var >= vdisp_size then st := x_sq;
y_var := 0;
else st := x_sq;
y_var := y_var +1;
end if;
when others => st:=init;
end case;
coordinate := x_var + y_var*hdisp_size;
if x_var >=0 and x_var < 15 and
y_var >= 0 and y_var < 44 then
color_var := red_c;
elsif x_var >= 20 and x_var < 300 and
y_var >= 40 and y_var < 200 then
color_var := cyan_c;
elsif x_var >= 300 and x_var < 320 and
y_var >= 200 and y_var < 240 then
color_var := green_c;
else
color_var := black_c;
end if;
end if;
write_data_s <= color_var;
write_addr_s <= conv_std_logic_vector(coordinate, write_addr_s'length);
end process;


--==========================

Next, I should try adding another Bram that will hold on to the objects.  As a small example I must use the coe file that was used to make mario.  Then I will have to use easyBMP to convert more pictures into their bram equivalent.

quarter VGA (qVGA) 320 by 240 resolution

The default for vga is 640 by 480.  There are tons of documentation about how to get this timing correct and there are tons for larger resolutions.

However, there is hardly any mention of 320 by 240.

The reason I needed that resolution was because I needed to make a pixel matrix that would hold the color
value for each coordinate.  The pixel matrix exists in memory and unfortunately my spartan 6 doesn't have a lot of it.

The purpose of this blog entry is to document the qVGA timings that I have found through trial and error.


 hdisp_size = 320;  //This specifies the width of the screen
 hpw_size = 48; // pulse width
 hbp_size = 28; // back porch
 hfp_size = 4; //front porch

 hsync_period = 400//this specifies the number of clock ticks before going back to zero.  ie. 0 to 399


 vdisp_size = 240; // this specifies the height of the screen
 vpw_size = 1; //pulse width
 vbp_size = 15; // back porch
 vfp_size = 4; // front porch

 vsync_period =  260;// this specifies the number of clock ticks before going back to zero. ie 0 to 259

The h clock will tick every 80 ns
the v clock will tick every 63.84 us

The screen I was using was quite finicky when it came to the right pw, bp, or fp values, but after awile I started to notice a trend.

The screen should refresh 60 hz to 60.5 hz.
In reality I got 60.48 hz.

The numbers MUST conform to that timing constraint or else it will not work properly.
When the screen resolution was 640 wide, we would need to count up to 800.
At first I mirely set it to 320 wide and made it count to 800 (and increased the bp,pw,and fp to accomodate it).    This made big black margins
to appear on the left and right side of the screen

The same happened with the height.  Originaly i had it at 480 and had it count to 521.
Then I changed it to 240 and increased the bp,pw, and fp to keep the counter counting up to 521.
This made top and bottom margins.

Although it worked, i was more interested in taking over the entire screen.

The h_sync had to cycle every 32 us. which means that you have to count from 0 to 399 in 32 us.
originally would count to that number in 16us so I basically clock divided the h clk.

The v_sync had to cycle every 16640 us.  which means that you have to count from 0 to 259 in 16640 us.
I also clock divided the v_clk.


*****
important observation
******
for a long time I had been missing a margin.  I had thought my value for the fp,bp, or pw were offset.
but in reality, it was because I was sending color when I wasn't suppose to.  I tried sending the color outside of the 320*240 grid and as a result, the screen tried to adjust to fit it in.  The screen doesn't know where coordinate (0,0) is located so it will need to guess based on when it gets a color.  If this theory is true,
then it would be wise to always place a background.  A very light background.

VGA with add shape, add image, with matrix transformations

After getting the VGA to work I've started to come up with a plan to
created a device that would show wither shapes or images to the screen.
I've decided that all the objects would exist as data on BRAM

At first I thought of using a "pixel matrix" which was a 640 by 480
std_logic_vector.  It was huge and synthesis too an extremely long
time.  I am not sure how long it would have taken because I did not
let it finish.  After 2 hours of letting it freeze and go.  I had to quit it.
If it was this complicated for the machine then it means I am doing
something really inefficient.

So then I thought of using bram.  I was hesitant because i remembered
that memory took a long time to synthesis too.  But BOY was a wrong.
It only took a few minutes to synthesize a memory of my choosing.
first I made a a bram  1 by 307200.  It worked but this method would
only allow black and white.  I tried 8 by 307200 , but unfortunately
I hit my constraint.  There wasn't enough ram in my device to do this.

Several ideas bounced around in my head.  maybe i could use some sort
of mux that would play with an FPGA object.

I scrapped that idea because it would lead to something rigid.  If I
wanted to add shapes via UART, then I would need to think of a
different plan.

The new plan was to get rid of the pixel matrix idea.  The idea was
to use opcodes to specify what shape it was or what image it was.
It would include the coordinates, the dimensions and/or some other pixel
data.  The rest of it would be generated by the fpga using a fancy
algorithm.  An algorithm that I haven't thought of at this moment.

There are two categories, shapes and images.  Images take up quite a lot of
space because each pixel needs to be accounted for.  Shapes don't take up
much space at all.  A square would probably take at most two words
to describe.

The header for both would have the same format.  The opcode would
differ in order to tell the control what it is dealing with.
Below is a pictorial version of what I am talking about:
                                 
                                   | upper left corner |
opcode | scale | rotate | x coord | y coord |
4 bit     | 3 bits | 5 bits | 10 bits   | 10 bits  |

A header would be one word and would contain the upper left corner,
the rotation factor and the scale factor.  These three pieces of information
are extremely value able and would be used in the matrix transformations.

These three pieces would have to affect the pixel data what would come
after it.  Remember how I said that a square would take as little as two
lines?  well the next line would be its pixel data.  One way i can do it
is by specifying the width and the height.  However, if I want a shape
that is more custom I would have to specify the coordinates of the points.
Here is a new idea that might be better.

What if I wanted to make a parallelogram?  The width and the height
would be used to set the dimensions of the "plate" that the shape
will be on.   The points would exist in relation to the "plate"
if it was a 10 by 10 plate then I would specify the points as if I was
drawing on a 10 by 10 grid.

ie.  a triangle on the 10 by 10 grid  p1(2, 4) p2(0,10) p3(10,10)

When I move the triangle all I have to do is move the plate.  the points
would not have to change.  They are in relation to the plate, so if the plate
moves, the points move with it.  Everything would be in relation to that
upper left corner.  So theoretically, I should be able to rotate everything
and scale it.

images would be a similar story.except that all the pixels of the image would
be considered a point.  it would be a point on the "plate".  the points
would exist in relation to the upper left corner.  The side effect is that they
take up a lot of space.

in order to deal with this i needs to separate the shapes from the
images.  the images would have a larger page and the shapes would
have a smaller page.

I believe the limit is 900000 bits  so i have to divide it up in a way that
can help share the ram.

for shapes
32*(8)*(2**6) = (wordsize)(shape _lines)(shape pages)

each word is 32 bits.  the number of lines it is allowed is 8.  the number
of pages allowed is 64.  that would take 16k bits.

for images
32*(2**10)*(2**3)  = (word size)(image_lines)(image pages)

each word is 32 bits.  The number of lines it is allowed is 1024.
The number of pages allowed is 8.  That would take about 262144 bits

======
before i forget, the line right after the header should be about the
dimension of the plate.  it will always be a rectangle.

So tell me again about how the pixel data is suppose to look like?
I have two choices

choice 1
opcode | color | relative x | relative y |
4 bits    | 8 bits | 10 bits     | 10 bits     |

choice 2
opcode |    | color |    | color |    | color |
4 bits    | 2 | 8 bits | 1| 8 bits | 1 | 8 bits |

choice two would be ideal for space saving.  It might be good
for images.  It would be as if I am naming each color of pixel
from left to right; top to bottom.

The first choice would name a spot on the plate to color.
This would be best for shapes.  but it can also be used for images.
This would be a good choice because everything would be similar
and require less components to decipher it.  it also brings ups the
possibility of shading it in a polygons.


=====
Eventually I'll have to decide  on which one to pick in order flesh everything out.

Once I have it I can start fleshing out the components that I will need in order to make this dream a reality.  Gosh, I never thought I'd be diving in to operating system concepts
just to do this.  I'm glad that i am thought.  It makes me think
as a computer scientist.  I'm glad that this very important class
is coming back up.  It lets me practice the idea of paging.

HA! maybe this is a step toward making an of run onto of the
FPGA after i get a cpu to start running on it.  I could probably use
the BOOK's code and from there I dunno I haven't thought that
far out.

vga

It is a wonderful day because I have figured out the vga timer once again.  

The problem probably had something to do with the PES clock.

The first few moments, the output would be undefined.  The

screen I tested on probably saw that undefined ness and put up

a flag that said "problem" and refused to work.  After I took

care of that problem it all started to work.  Its funny how that little 

small start of undefined signal messed everything up.

Another thing that contributed to the problem was that the h counter and

v counter were not counting at the right time.  The v counter should 

increment when ever the h counter was reset to zero.  But for some 

reason, it would increment when h counter reached 400.  

These two problems were eventually solved.  The first one was solved 

by modifying the pes_clock such that  clock_out was given its value soon

after starting up.  It used to have to wait until the process reached its 

max count before giving it a value.

The second was solved by making the the v counter count on the

falling edge of the v_clk.  Even though it gave a warning during synthesis

all I care is that it works.

Mixing VHDL and verilog modules

INTRO
I have successfully been able to mix both VHDL modules and Verilog modules together.  Honestly it is a lot easier then I had thought it would be.  Since I could not find detailed examples of this phenomenon, I had to experiment with how it would work out.  The examples that I found were all wrong, but they gave enough of a hint to figure it out on my own.  I'm quite sure there are many people that need to know this so if you are here, you are in a good place.

ABSTRACT
A simple Verilog top module was crafted as a 2 bit full adder.  The internal components would be a verilog one bit adder and VHDL one bit adder.  They got connected in the verilog top module and were successfully testbenched and synthesized.  Did I mention that I used a testbench written in vhdl to test the 2 bit FA verilog top module?

Also as a second pass, I created a simple VHDL top module that was crafted as a 2 bit full adder.  The internal components would ALSO be a verilog 1 bit full adder and vhdl 1 bit full adder.  They got connected in the vhdl top module and they successfully testbenched and synthesized.

CODE
Below is the code that was used to create the described 2 bit adders.  Hopefully it will demonstrate how easy it is to go from one language to the other.
=====================
-- 1 bit FA in VHDL
--------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FA_VHDL is
    Port ( A,B,CIN : in  STD_LOGIC;
           COUT,S : out  STD_LOGIC);
end FA_VHDL;
architecture Behavioral of FA_VHDL is
begin
--concurrent implementation of a 1 bit full adder.
--Statements outside of a process are considered concurrent
S <= A xor B xor CIN;
COUT <= (A and B) or (A and CIN) or (B and CIN);

--Alternative implementation with a use of sensitivity list.
--This block will only execute when the items in the sensitivity list change
-- FA : process (A,B,CIN)
-- begin
-- S <= A xor B xor CIN;
-- COUT <= (A and B) or (A and CIN) or (B and CIN);
-- end process;
end Behavioral;

=====================
--1 bit FA in verilog
--------------------------------

`timescale 1ns / 1ps
module FA_v(
A,B,CIN,
COUT,S);
//------------
input A,B,CIN;
output COUT, S;
// reg COUT,S; // uncomment if using "always block"
//----
//This makes the logic happen continuously
assign S = A ^ B ^ CIN;
assign COUT =  (A & B)  | (A & CIN) | (B & CIN);

//Alternative implementation with a use of sensitivity list.
//This "always block" will only execute when the items in the sensitivity list change
// always @ (A or B or CIN)
// begin
// S <= A ^ B ^ CIN;
// COUT <=  (A & B)  | (A & CIN) | (B & CIN);
// end
endmodule


=====================
--2 bit FA in verilog with internal components: 1 bit verilog fa and 1 bit vhdl fa
--------------------------------

`timescale 1ns / 1ps
`default_nettype none

module Verilog_2bit_adder(
A2b,B2b,CIN2b,
COUT2b,S2b
);
//define pins
input [1:0] A2b,B2b;
input CIN2b;
//define ports
output COUT2b;
output [1:0] S2b;
//Specify internal wire
wire carry_w;
FA_v verilog_full_adder(
.A    (A2b[0]), // ".A" specifies the Pin of the component. "A2b[0]" specifies the thing that is connecting to that pin
.B    (B2b[0]),
.CIN  (CIN2b),
.COUT (carry_w),
.S    (S2b[0])
); //for bit0
FA_VHDL VHDL_full_adder(
.A    (A2b[1]),
.B    (B2b[1]),
.CIN  (carry_w),
.COUT (COUT2b),
.S    (S2b[1])
);//for bit1
endmodule


=====================
--2 bit FA in VHDL with internal components: 1 bit verilog fa and 1 bit vhdl fa
--------------------------------

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;

entity VHDL_2bit_adder is
   port ( A2b    : in    std_logic_vector (1 downto 0);
          B2b    : in    std_logic_vector (1 downto 0);
          CIN2b  : in    std_logic;
          COUT2b : out   std_logic;
          S2b    : out   std_logic_vector (1 downto 0));
end VHDL_2bit_adder;

architecture BEHAVIORAL of VHDL_2bit_adder is
   signal carry_s : std_logic;
   component FA_v
      port ( A    : in    std_logic;
             B    : in    std_logic;
             CIN  : in    std_logic;
             COUT : out   std_logic;
             S    : out   std_logic);
   end component;
 
   component FA_VHDL
      port ( A    : in    std_logic;
             B    : in    std_logic;
             CIN  : in    std_logic;
             COUT : out   std_logic;
             S    : out   std_logic);
   end component;
 
begin
   verilog_full_adder : FA_v
      port map (
               A=>A2b(0),
               B=>B2b(0),
               CIN=>CIN2b,
               COUT=>carry_s,
               S=>S2b(0)
);
 
   VHDL_full_adder : FA_VHDL
      port map (
               A=>A2b(1),
               B=>B2b(1),
               CIN=>carry_s,
               COUT=>COUT2b,
               S=>S2b(1)
);
 
end BEHAVIORAL;




=====================
--vhdl test bench
--------------------------------

-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY VHDL_two_bit_adder_TB IS
END VHDL_two_bit_adder_TB;

ARCHITECTURE behavior OF VHDL_two_bit_adder_TB IS
    -- Component Declaration for the Unit Under Test (UUT)
    --COMPONENT Verilog_2bit_adder --testing uncomment to test verilog
COMPONENT VHDL_2bit_adder
    PORT(
         A2b : IN  std_logic_vector(1 downto 0);
         B2b : IN  std_logic_vector(1 downto 0);
         CIN2b : IN  std_logic;
         COUT2b : OUT  std_logic;
         S2b : OUT  std_logic_vector(1 downto 0)
        );
    END COMPONENT;
   --Inputs
   signal A2b : std_logic_vector(1 downto 0) := (others => '0');
   signal B2b : std_logic_vector(1 downto 0) := (others => '0');
   signal CIN2b : std_logic := '0';

  --Outputs
   signal COUT2b : std_logic;
   signal S2b : std_logic_vector(1 downto 0);

signal clock : std_logic := '0';
   constant clock_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
--      uut: Verilog_2bit_adder PORT MAP ( --uncomment if using verilog component
        uut: VHDL_2bit_adder PORT MAP ( -- uncomment if using VHDL component
          A2b => A2b,
          B2b => B2b,
          CIN2b => CIN2b,
          COUT2b => COUT2b,
          S2b => S2b
        );

   -- Clock process definitions
   clock_process :process
   begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;
A_loop: for A in 0 to 3 loop
B_loop: for B in 0 to 3 loop
CIN_loop: for CIN in 0 to 1 loop
A2b <= conv_std_logic_vector(A, 2);
B2b <= conv_std_logic_vector(B, 2);
if CIN = 1 then
CIN2b <= '1';
else
CIN2b <= '0';
end if;
wait for clock_period;
assert (A+B+CIN = conv_integer(COUT2b&S2b)) report "This isn't right" severity error;
end loop CIN_loop;
end loop B_loop;
end loop A_loop;
      -- insert stimulus here

      wait;
   end process;

END;

python in xcode 4

1. Open Xcode 4.
2. In the menu bar, click "File" → "New" → "New Project…".
3. Select "Other" under "Mac OS X".
4. Select "External Build System" and click "Next".
5. Enter the product name.
6. For the "Build Tool" field, type in /usr/local/bin/python3 for Python 3 or /usr/bin/python for Python 2 and then click "Next". Note that this assumes you have Python installed in the typical location(s). if you are unsure as to where your Python executables are enter these commands into Terminal: which python3 and which python.
7. Choose where to save it and click "Create".
8. In the menu bar, click "File" → "New" → "New File…".
9. Select "Other" under "Mac OS X".
10. Select "Empty" and click "Next".
11. Navigate to the project folder (it will not work, otherwise), enter the name of the Python file (include the ".py" extension), and click "Save".
12. In the menu bar, click "Product" → "Edit Scheme…".
13. Click "Run" in the left column.
14. In the "Info" tab, click the "Executable" field and then click "Other…".
15. Navigate to the executable from Step 6. You may need to use ⇧⌘G to type in the directory if it is hidden.
16. Select the executable and click "Choose".
17. For the "Debugger" field, select "None".
18. In the "Arguments" tab, click the "Base Expansions On" field and select the target that is named the same as your project.
19. Click the "+" icon under "Arguments Passed On Launch". You may have to expand that section by clicking on the triangle pointing to the right.
20. Type in $(SOURCE_ROOT)/ and then the name of the Python file you want to test. Remember, the Python program must be in the project folder. Otherwise, you will have to type out the full path (or relative path if it's in a subfolder of the project folder) here. If there are spaces anywhere in the full path, you must include quotation marks at the beginning and end of this.
21. Click "OK".
22. Start coding.

Note that if you open the "Utilities" panel, with the "Show the File inspector" tab active, the file type is automatically set to "Default - Python script". Feel free to look through all the file type options it has to gain an idea as to what all it is capable of doing. The method above can be applied to any interpreted language. As of right now, I have yet to figure out exactly how to get it to work with Java; then again, I haven't done too much research. Surely there is some documentation floating around on the web about all of this.

Say, "Hello, code completion, auto-indentation, and syntax highlighting." Note that it's not as advanced as it is with C, C++, or Objective-C but it is better than using IDLE in my opinion.

---------------------

original link
http://stackoverflow.com/questions/5276967/python-in-xcode-4